As the area occupied by cell regions of semiconductor devices such as dynamic random access memories (DRAMs) has decreased with the increased integration density of the semiconductor devices, contact resistance has tended to increase because the area of a semiconductor substrate exposed by the contact hole typically is decreased. Because of the decreased contact hole size, a conductive layer for filling the contact hole may short to adjacent structures such as gate electrodes, for example, when misalignment occurs during photolithographic processes used in forming the contact hole.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional method for forming a self-aligned contact hole. A gate insulating film 20, e.g., silicon dioxide, is formed on a semiconductor substrate 10. Then, a gate conductive layer, for example, a polycrystalline silicon layer doped with impurities, is formed on the entire surface of the substrate 10 on which the gate insulating film 20 is formed. A capping layer, for example a silicon nitride film or a silicon oxide film, is formed on the gate conductive layer. Capping layer patterns 40 and the gate electrodes 30 are then formed by patterning the capping layer and the gate conductive layer so as to expose the gate insulating film 20. Here, the gate electrode 30 and the capping layer pattern 40 construct a gate pattern 45, with the gate patterns 45 being separated from each other by a predetermined distance. Subsequently, an insulating film 50, for example, a silicon nitride film, is formed on the substrate, covering the gate patterns 45.
Referring to FIG. 2, an interlayer dielectric film whose surface is flat, for example, a borophosphosilicate glass (BPSG) film or an undoped silicate glass (USG) film, is formed on the spacer insulating film 50. A photosensitive layer pattern 65 is then formed having a hole for exposing the interlayer dielectric film positioned above the region between the gate patterns 45 and the edge of the capping layer pattern 40. An interlayer dielectric film pattern 60 is formed by anisotropically etching the interlayer dielectric film so as to expose the spacer insulating film 50 using the photosensitive layer pattern 65 as an etching mask.
Referring to FIG. 3, a spacer insulating film pattern 50b and a gate insulating film pattern 20a are formed by sequentially etching the modified spacer insulating film 50a and the gate insulating film 20 using the photosensitive layer 65 as an etching mask, forming a contact hole h for exposing a predetermined region of the semiconductor substrate 10 positioned between the gate patterns 45. In forming the interlayer dielectric film pattern 60, a portion of the spacer insulating film 50a adjacent the shoulder A of the gate pattern 45 may be etched an excessive amount due to a sputtering effect during the anisotropic etching of the interlayer dielectric film, even if the etching selection ratio of the interlayer dielectric film with respect to the spacer insulating film 50 is large (see J. Gambino et al., "A Si3N4 Etch Stop Process for Borderless Contacts in 0.25 .mu.m Devices", IEEE V-MIC Proc. 1995, pp. 558-564). The capping layer 40 may be etched, as the thickness of the modified spacer insulating film 50a formed on the shoulder A of the gate pattern 45 is decreased. Accordingly, a modified capping layer 40a may be formed which exposes a predetermined region of the upper surface of the shoulder of the gate electrode 30, resulting in a modified gate pattern 45a. The upper side wall of the gate electrode 30, as well as a predetermined region of the upper surface of the shoulder of the gate electrode 30, may be exposed because the spacer insulating film pattern 50b does not completely cover the entire surface of the side wall. A spacer 50c on the side wall of the capping layer pattern 40 and the gate electrode 30 also may not be completely formed. As a consequence, a conductive layer formed in the contact hole h and contacting the semiconductor substrate 10 may be also connected to the gate electrode 30.
Unfortunately, there tend to be limitations to increasing the thickness of the capping layer pattern 40 in order to prevent a predetermined region of the upper surface of the shoulder of the gate electrode 30 from being exposed. The surface step coverage of the substrate on which the gate patterns are formed tends to increase when the capping layer pattern 40 is thickened, thus generating difficulties in flattening the interlayer dielectric film. Therefore, it is generally not desirable to make the capping layer pattern 40 thick.